DRAM, FLASH, and SRAM are the three major conventional semiconductor memories on the market. The manufacturing cost of DRAM is the lowest. However, in addition to shortcomings such as the need for refreshment, relatively low speed and high power consumption, DRAM is volatile. Consequently, a DRAM loses data when the power is turned off. FLASH memory is non-volatility, but is very slow. The write cycle endurance for a FLASH memory is less than one million cycles. This write cycle endurance limits the application of FLASH memories in some high data rate market. SRAM is a fast memory. However, SRAM is volatile and takes too much silicon area per cell. In search of a universal random access memory that offers high speed, non-volatility, small cell area, and good endurance, many companies are developing thin film Magnetic Random Access Memories (MRAM).
Conventional MRAMs can be fabricated with a memory cells using a variety of magnetic elements, such as an Anisotropic Magnetoresistance (AMR) element, a Giant Magnetoresistance (GMR) element, and a Magnetic Tunneling Junction (MTJ) stack. For example, a conventional MTJ stack is relatively simple to manufacture and use. Consequently, an MRAM is used as the primary example herein.
The magnetic field for changing the orientation of the changeable magnetic vector is usually supplied by two conductive lines that are substantially orthogonal to each other. When electrical current passes through the two conductive lines at the same time, two magnetic fields associated with the current in the two conductive lines act on the changeable magnetic vector to orient its direction.
FIG. 1A depicts a portion of a conventional MRAM 1. The conventional MRAM includes conventional orthogonal conductive lines 10 and 12, conventional magnetic storage cell having a MTJ 30 and conventional transistor 13. In some designs, the conventional transistor 13 is replaced by a diode, or completely omitted, with the conventional MTJ cell 30 in direct contact with the conventional word line 10. The conventional MRAM 1 utilizes a conventional magnetic tunneling junction (MTJ) stack 30 as a memory cell. Use of a conventional MTJ stack 30 makes it possible to design an MRAM cell with high integration density, high speed, low read power, and soft error rate (SER) immunity. The conductive lines 10 and 12 are used for writing data into the magnetic storage device 30. The MTJ stack 30 is located on the intersection of and between conventional conductive lines 10 and 12. Conventional conductive line 10 and line 12 are referred to as the conventional word line 10 and the conventional bit line 12, respectively. The names, however, are interchangeable. Other names, such as row line, column line, digit line, and data line, may also be used.
The conventional MTJ 30 stack primarily includes the free layer 38 with a changeable magnetic vector (not explicitly shown), the pinned layer 34 with a fixed magnetic vector (not explicitly shown), and an insulator 36 in between the two magnetic layers 34 and 38. The insulator 36 typically has a thickness that is low enough to allow tunneling of charge carriers between the magnetic layers 34 and 38. Layer 32 is usually a composite of seed layers and an antiferromagnetic (AFM) layer that is strongly coupled to the pinned magnetic layer. The AFM layer included in the layers 32 is usually Mn alloy, such as IrMn, NiMn, PdMn, PtMn, CrPtMn, and so on. The AFM layer is typically strongly exchanged coupled to the pinned layer 34 to ensure that the magnetic vector of the pinned layer 34 is strongly pinned in a particular direction.
When the magnetic vector of the free layer 38 is aligned with that of the pinned layer 34, the MTJ stack 30 is in a low resistance state. When the magnetic vector of the free layer 38 is antiparallel to that of the pinned layer 34, the MTJ stack 30 is in a high resistance state. Thus, the resistance of the MTJ stack 30 measured across the insulating layer 34 is lower when the magnetic vectors of the layers 34 and 38 are parallel than when the magnetic vectors of the layers 34 and 38 are in opposite directions.
Data is stored in the conventional MTJ stack 30 by applying a magnetic field to the conventional MTJ stack 30. The applied magnetic field has a direction chosen to move the changeable magnetic vector of the free layer 30 to a selected orientation. During writing, the electrical current I1 flowing in the conventional bit line 12 and I2 flowing in the conventional word line 10 yield two magnetic fields on the free layer 38. In response to the magnetic fields generated by the currents I1 and I2, the magnetic vector in free layer 38 is oriented in a particular, stable direction. This direction depends on the direction and amplitude of I1 and I2 and the properties and shape of the free layer 38. Generally, writing a zero (0) requires the direction of either I1 or I2 to be different than when writing a one (1). Typically, the aligned orientation can be designated a logic 1 or 0, while the misaligned orientation is the opposite, i.e., a logic 0 or 1, respectively.
FIG. 1B depicts a conventional method 50 for reading data from the conventional MRAM 1. The method 50 is depicted in the context of FIG. 1A. Referring to FIGS. 1A and 1B, during reading, the conventional transistor 13 is turned on so that a small tunneling current can flow through the conventional MTJ stack 30, via step 52. A current is provided and passed through the MTJ 30 stack, via step 54. Thus, the current passes from one magnetic layer 34 or 38 to the other magnetic layer 38 or 34, respectively. The resistance of the MTJ stack 30 is determined, via step 56. The resistance of the MTJ stack 30 can be determined in step 56 by measuring the voltage across the MTJ stack 30 for the current provided in step 54. Alternatively, the voltage across the MTJ stack can be set and the current through the MTJ measured in step 56. The resistance of a separate reference element is determined, via step 58. Preferably, the separate reference element has a magnitude that is the average of the high resistance and the low resistance of the MTJ stack 30. Typically, the resistance of the separate reference element is between the resistances of the high and low resistance states of the MTJ stack 30. Note that for clarity, the separate reference element is omitted from the MRAM 1. However, the separate reference element typically resides in a separate location and is isolated from each of the MTJ stacks, such as the MTJ stack 30. Based on the resistance of the MTJ stack 30 and the resistance of the separate reference element, the state of the MTJ stack 30 is determined, via step 60. In particular, if the resistance of the MTJ stack 30 is lower than the resistance of the separate reference element, then the MTJ stack 30 is determined to be in the low resistance state. If the resistance of the MTJ stack 30 is higher than the resistance of the separate reference element, then the MTJ stack 30 is determined to be in the high resistance state. Step 60, therefore, compares the resistance of the MTJ stack 30 to the resistance of the separate reference element. Thus, it can be determined whether the MTJ stack 30 stores a zero or a one.
Although the conventional method 50 functions in principle, one of ordinary skill in the art will readily recognize that in practical applications, the signal level (the difference in the resistance between the low resistance state and the high resistance state) should be larger than the variations of resistance variations among the data cells, relative to the separate reference element. As the size of memory cell and, therefore, the MTJ stack 30, scales down, and the tunneling layer 36 in the MTJ stack 30 becomes thinner, variations in resistance among the MTJ stacks 30 adversely affect the ability of the conventional method 50 to adequately distinguish between the low and high resistance states of the MTJ stack 30. Thus, the conventional method 50 poses read-back reliability challenges for MRAM scalability.
Accordingly, what is needed is a method and system for providing a read scheme having improved reliability and reduced susceptibility to variations among storage elements. The present invention addresses such a need.